During operation of a wireless communication system when transmitting data it is necessary to decode various channel codes that are used for forward error correction. Typical channel codes, such as those used in 3G systems and WiMAX, are turbo codes, duo-turbo codes, and low density parity check (LDPC) codes.
Higher transmitted data rates imply the presence of a faster channel decoder at a receiver. A simple solution to address this need is to increase a clock frequency of a receiver decoder to achieve a required data rate. However, the use of a high clock frequency requires the decoder, such as one implemented in an integrated circuit such as an ASIC, to consume more power which, in a portable battery powered device, is a distinct disadvantage.
Another possible solution is to apply parallel processing for decoding. However, this approach raises a problem related to multiple access of data in two different access orders. While it may be straightforward to design a multiple access scheme for one access order, in the case of turbo codes and low density parity check codes, the multiple access scheme must be usable at least for two independent access orders without an access collision.
One possible technique to address the multiple access problem is to implement a row or bank of turbo decoders without internal multiple access capability. This technique may be adequate when data rates are not high, e.g., less than 20, Mbps.
Another possible technique to establish parallel processing is to design an interleaver of a code such that the interleaver supports some kind of multiple access schemes. An example of this kind approach is described by Takeshita, “On maximum contention-free interleavers and permutation polynomials over integer rings”, IEEE Trans. Inform. Theory, vol. 52, no. 3, pp. 1249-1253, March 2006. A weakness of this technique is that it is not applicable to existing systems. Another weakness is that a type of parallel processing depends on an interleaver of a code and one cannot modify it afterwards
Yet another multiple access technique is described by Benedetto et al., “Design issues on the parallel implementation of versatile, high-speed iterative decoders”, Turbo-Coding-2006, Apr. 3-7, 2006, Munich. Reference can also be had to an approach described by Tarable et al., “Mapping Interleaving Laws to Parallel Turbo and LDPC Decoder Architectures”, IEEE Transactions on Information Theory, Vol. 50, No. 9, September 2004.
Tarable et al. construct a mapping such that it is possible to process data in parallel both in a linear order and in an interleaved order without an access collision. Moreover, their solution is independent of the interleaver, that is, their method can be applied to any interleaver without restrictions. However, a drawback to this approach is that it requires very large switches (multiplexers) for implementation. Another drawback is that the method must be able to reorder data from any order to any order. For example, to accomplish parallel processing of degree 4, the decoder needs to generate 4!=1*2*3*4=24, orders. If the degree of parallel processing is 8, there are 8!=40320, cases to generate.
Clearly, a deficiency of this approach is that the algorithm used to generate the mapping function is quite complex. Also the algorithm does not guarantee a simple network for routing data.